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Design and optimization of 22nm NMOS transistor

In this paper, we investigate the effects of four process parameters and two process noise parameters on the threshold voltage (V th) of a 22nm NMOS transistor. We used TiO 2 as the high-k material to replace the SiO 2 dielectric. The NMOS transistor was simulated using the fabrication tool ATHENA a...

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書誌詳細
主要な著者:	Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Majlis B.Y., Salehuddin F.
その他の著者:	36570222300
フォーマット:	論文
出版事項:	2023
主題:	22nm NMOS ANOVA Orthogonal array Taguchi method Threshold voltage
タグ:	タグ追加タグなし, このレコードへの初めてのタグを付けませんか!

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