Scaling down of the 32 nm to 22 nm gate length NMOS transistor

• Main Authors: Afifah Maheran, A.H., Menon, P.S., Ahmad, I., Elgomati, H.A., Majlis, B.Y., Salehuddin, F.
• Published: 2017
• Online Access: http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5224

In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate in...