Threshold voltage optimization in a 22nm High-k/Salicide PMOS device

• Main Authors: Afifah Maheran A.H., Menon P.S., Ahmad I., Yusoff Z.
• Other Authors: 36570222300
• Format: Conference paper
• Published: 2023
• Subjects: 22 nm gate length PMOS; high-k/SALICIDE; Taguchi Method; threshold voltage; Optimization; Signal to noise ratio; Silicides; Taguchi methods; Titanium dioxide; Electrical characterization; Gate electrode resistance; Gate length; High-k dielectric layers; High-permittivity material; International Technology Roadmap for Semiconductors; Signaltonoise ratio (SNR); Threshold voltage

In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide...