Modelling of process parameters for 32nm PMOS transistor using Taguchi method

• 主要な著者: Elgomati H.A., Majlis B.Y., Hamid A.M.A., Susthitha P.M., Ahmad I.
• その他の著者: 36536722700
• フォーマット: Conference paper
• 出版事項: 2023
• 主題: 32nm PMOS; ANOM; ANOVA; compensation implantations; L18 orthogonal array; Taguchi Method; Threshold voltage; Analysis of variance (ANOVA); CMOS integrated circuits; Computer simulation; Taguchi methods; Analysis of means; Circuit performance; CMOS technology; Device parameters; Electrical characterization; Fabrication tool; Mean values; Modelling of process; Nanometer level; Noise factor; Objective functions; pMOS transistors; Process noise; Process parameters; Robust designs; S/N ratio; Taguchi; Mathematical models

As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transis...