Investigation of parasitic capacitance in 14nm twin silicon nanowire field effect transistor
Saved in:
Main Authors: | Johari, Zaharah, Paraman, Norlina, Alias, Nurul Ezaila, Agussalim, Alia Noor Fiswani |
---|---|
Format: | Conference or Workshop Item |
Published: |
2018
|
Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/83153/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Optimization of 3-D N-channel twin silicon nanowire MOSFET
by: Alias, Nurul Ezaila, et al.
Published: (2015) -
Characterization of silicon nanowire transistor
by: Al Ariqi, Hani Taha, et al.
Published: (2019) -
Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
by: Naif, Yasir Hashim
Published: (2013) -
Carbon nanotube and silicon nanowire nanoscale field effect transistor modeling
by: Ahmadi, Mohammad Taghi
Published: (2010) -
Impact of device parameter variation on the electrical characteristic of n-type junctionless nanowire transistor with high-k dielectrics
by: Sule, Mohammed Adamu, et al.
Published: (2020)