Optimization of 3-D N-channel twin silicon nanowire MOSFET
Abstract—Twin Silicon Nanowire N-channel MOSFET (n-TSNWFET) is an advanced nanotechnology which is believed to be the smallest structure of CMOS devices as well as approaching their downsized limits according to the Moore’s Law. In this work, the optimization of n-channel TSNWFET is described and ex...
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Main Authors: | , , |
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Format: | Conference or Workshop Item |
Published: |
2015
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Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/62131/ http://mne2015.org/ |
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