Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.
Silicides; Silicon on insulator technology; Taguchi methods; Current optimization; Device performance; Fabrication process; International technology; L9 orthogonal arrays; Performance parameters; Process parameters; Silicon-on- insulators (SOI); Hafnium oxides
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| Main Authors: | , , , , , , , , |
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| Format: | Conference Paper |
| Published: |
Institute of Physics Publishing
2023
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