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Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.

Silicides; Silicon on insulator technology; Taguchi methods; Current optimization; Device performance; Fabrication process; International technology; L9 orthogonal arrays; Performance parameters; Process parameters; Silicon-on- insulators (SOI); Hafnium oxides

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Main Authors: Afifah Maheran A.H., Firhat E.N., Salehuddin F., Mohd Zain A.S., Ahmad I., Noor Faizah Z.A., Menon P.S., Elgomati H.A., Roslan A.F.
Other Authors: 36570222300
Format: Conference Paper
Published: Institute of Physics Publishing 2023
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spelling my.uniten.dspace-254242023-05-29T16:09:15Z Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method. Afifah Maheran A.H. Firhat E.N. Salehuddin F. Mohd Zain A.S. Ahmad I. Noor Faizah Z.A. Menon P.S. Elgomati H.A. Roslan A.F. 36570222300 57217345087 36239165300 57217345950 12792216600 56395444600 57201289731 36536722700 57203514087 Silicides; Silicon on insulator technology; Taguchi methods; Current optimization; Device performance; Fabrication process; International technology; L9 orthogonal arrays; Performance parameters; Process parameters; Silicon-on- insulators (SOI); Hafnium oxides To acquire the optimal value of the performance parameter, a bilayer graphene with silicon on insulator (SOI) was enhanced and analyzed on 22 nm NMOS device. The device is made of Hafnium Dioxide (HfO2) as a high-k material whereas Tungsten Silicide (WSix) as a metal gate. The Silvaco software ATHENA and ATLAS modules were applied to simulate the fabrication process of virtual devices and to verify the device's electrical properties accordingly. The Taguchi L9 orthogonal array method was then used to enhance the device process parameters minimum leakage current (ILEAK) according to the International Technology Roadmap Semiconductor (ITRS) specification of 100nA/?m maximum range. The result from smaller-the-better (STB) for ILEAK is then reviewed by the percentage affecting the process parameter. The simulation result shows that the halo tilting angle is the most dominant factor for ILEAK optimization process. The optimized results indicate excellent device performance with ILEAK = 9.29746 nA/?m which is far lower than the prediction. � 2020 IOP Publishing Ltd. All rights reserved. Final 2023-05-29T08:09:15Z 2023-05-29T08:09:15Z 2020 Conference Paper 10.1088/1742-6596/1502/1/012047 2-s2.0-85087105139 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85087105139&doi=10.1088%2f1742-6596%2f1502%2f1%2f012047&partnerID=40&md5=8af66b405403bade61345faa52009bc5 https://irepository.uniten.edu.my/handle/123456789/25424 1502 1 12047 All Open Access, Bronze Institute of Physics Publishing Scopus
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description Silicides; Silicon on insulator technology; Taguchi methods; Current optimization; Device performance; Fabrication process; International technology; L9 orthogonal arrays; Performance parameters; Process parameters; Silicon-on- insulators (SOI); Hafnium oxides
author2 36570222300
author_facet 36570222300
Afifah Maheran A.H.
Firhat E.N.
Salehuddin F.
Mohd Zain A.S.
Ahmad I.
Noor Faizah Z.A.
Menon P.S.
Elgomati H.A.
Roslan A.F.
format Conference Paper
author Afifah Maheran A.H.
Firhat E.N.
Salehuddin F.
Mohd Zain A.S.
Ahmad I.
Noor Faizah Z.A.
Menon P.S.
Elgomati H.A.
Roslan A.F.
spellingShingle Afifah Maheran A.H.
Firhat E.N.
Salehuddin F.
Mohd Zain A.S.
Ahmad I.
Noor Faizah Z.A.
Menon P.S.
Elgomati H.A.
Roslan A.F.
Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.
author_sort Afifah Maheran A.H.
title Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.
title_short Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.
title_full Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.
title_fullStr Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.
title_full_unstemmed Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.
title_sort minimum leakage current optimization on 22 nm soi nmos device with hfo2/wsix/graphene gate structure using taguchi method.
publisher Institute of Physics Publishing
publishDate 2023
_version_ 1806428231533854720
score 13.214268

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