Taguchi method for p-MOS threshold voltage optimization with a gate length of 22NM
This paper describes the virtual design of a 22nm gate length p-type metal oxide semiconductor, PMOS. Silvaco, TCAD tools were used to fabricate the device design and to characterize the device’s electrical properties. Fixed field scaling rules are applied to obtain the transistor’s electrical par...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Universiti Malaysia Perlis
2023
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| Online Access: | http://eprints.utem.edu.my/id/eprint/27383/2/0169919062023231.PDF http://eprints.utem.edu.my/id/eprint/27383/ https://ijneam.unimap.edu.my/images/PDF/IJNEAM%20JAN%202023/Vol_16_January_2023_1-9.pdf |
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