Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate
0.5 µm gate length MOSFET is fabricated on Bond-and-Etch-Back Silicon-On-Insulator (BESOI) substrate using bulk CMOS technology. For the purpose of silicon layer thickness adjustment, sacrificial oxidation is implemented on the device layer of 1.5 ± 0.5 µm device layer and 2 µm buried oxide thicknes...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2002
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| Online Access: | http://psasir.upm.edu.my/id/eprint/18493/1/18493.pdf http://psasir.upm.edu.my/id/eprint/18493/ |
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