Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate

• Main Authors: Abdullah, Wan Fazlida Hanim, Mohd Sidek, Roslina, Mohd Saari, Shahrul Aman, Ahmad, Mohd Rais
• Format: Conference or Workshop Item
• Language: English
• Published: 2002
• Online Access: http://psasir.upm.edu.my/id/eprint/18493/1/18493.pdf; http://psasir.upm.edu.my/id/eprint/18493/

0.5 µm gate length MOSFET is fabricated on Bond-and-Etch-Back Silicon-On-Insulator (BESOI) substrate using bulk CMOS technology. For the purpose of silicon layer thickness adjustment, sacrificial oxidation is implemented on the device layer of 1.5 ± 0.5 µm device layer and 2 µm buried oxide thicknes...