Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as...
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Main Authors: | Noor Faizah, Z.A., Ahmad, I., Ker, P.J., Siti Munirah, Y., Mohd Firdaus, R., Md Fazle, E., Menon, P.S. |
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2017
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Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5185 |
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