Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as...
Saved in:
Main Authors: | , , , , , , |
---|---|
Format: | |
Published: |
2017
|
Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5185 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Be the first to leave a comment!