CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
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Main Author: | Assaad, Maher |
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Format: | Conference or Workshop Item |
Published: |
2007
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Subjects: | |
Online Access: | http://eprints.utp.edu.my/3503/1/MaherAssaad-paper1-2.pdf http://eprints.utp.edu.my/3503/ |
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