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CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC

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Bibliographic Details
Main Author: Assaad, Maher
Format: Conference or Workshop Item
Published: 2007
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utp.edu.my/3503/1/MaherAssaad-paper1-2.pdf
http://eprints.utp.edu.my/3503/
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id my.utp.eprints.3503
record_format eprints
spelling my.utp.eprints.35032017-01-19T08:27:00Z CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC Assaad, Maher TK Electrical engineering. Electronics Nuclear engineering 2007 Conference or Workshop Item PeerReviewed application/pdf http://eprints.utp.edu.my/3503/1/MaherAssaad-paper1-2.pdf Assaad, Maher (2007) CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC. In: International Symposium on System on Chip. http://eprints.utp.edu.my/3503/
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Institutional Repository
url_provider http://eprints.utp.edu.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Assaad, Maher
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
format Conference or Workshop Item
author Assaad, Maher
author_facet Assaad, Maher
author_sort Assaad, Maher
title CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
title_short CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
title_full CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
title_fullStr CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
title_full_unstemmed CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
title_sort cmos ic design and verilog-a modelling of 10-gb/s pll-based deserializer for inter-chip communication in soc
publishDate 2007
url http://eprints.utp.edu.my/3503/1/MaherAssaad-paper1-2.pdf
http://eprints.utp.edu.my/3503/
_version_ 1738655269750046720
score 13.15806

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