Implementation of Verilog HDL in Calculator Design with FPGA Simulation

• Main Authors: Shamsiah, Suhaili, Kayle Jacqueline, Kumar, Norhuzaimin, Julai, Maimun, Huja Husin, Mohd Faizrizwan, Mohd Sabri, Asrani, Lit
• Format: Article
• Language: English
• Published: IEEE 2020
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://ir.unimas.my/id/eprint/33604/1/Implementation%20of%20Verilog%20HDL%20in%20Calculator.pdf; http://ir.unimas.my/id/eprint/33604/; https://ieeexplore.ieee.org/document/9299337

A calculator is a device that can be found in daily life. This paper proposed the design of a calculator using Verilog HDL. A series of synthesizable Verilog code was created and simulated on Quartus II 15.0. The design of an 8-bit calculator can solve mathematical operations such as addition, subtr...