An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC
In this paper, an all-digital serializer circuit based on a novel frequency and delay locked-loop (F/DLL) clock multiplier is presented. The advantages of the proposed F/DLL are that, it simultaneously generates a high frequency signal from a low frequency reference signal and synchronizes the two s...
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| Main Authors: | , |
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| Format: | Article |
| Published: |
2011
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/7462/1/_pdf http://eprints.utp.edu.my/7462/ |
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