Characterization of 50 nm MOSFET with dielectric pocket
Characterizat ion of a metal-oxide-semi conductor field effect tran sistor incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE ) is demonstrated by using 2D numerical simulation. An analysis of 120 nm and 50 nm channel length (LJ wit h DP incorp orated between the chann...
Saved in:
Main Authors: | Fauzan, Zul Atfyi, Saad, Ismail, Ismail, Razali |
---|---|
Format: | Article |
Language: | English |
Published: |
Malaysian Institute of Physics
2007
|
Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/8046/2/%5B093-098%5D-zul.pdf http://eprints.utm.my/id/eprint/8046/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET)
by: Ismail, Razali, et al.
Published: (2007) -
Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET)
by: M. N., Zul Atfyi Fauzan, et al.
Published: (2008) -
Process and Characterization of Strained Silicon MOSFET Incorporating Dielectric Pocket (SDP-MOSFET)
by: Mohammed Napiah, Zul Atfyi Fauzan, et al.
Published: (2011) -
Current-Voltage Analysis of Nanoscale Planar and Vertical MOSFET Incorporating Dielectric Pocket
by: Mohammed Napiah, Zul Atfyi Fauzan, et al.
Published: (2011) -
Design and characterization of nanoscale metal -oxide- semiconductor field effect transistor incorporating dielectric pocket
by: Mohammed Napiah, Zul Atfyi Fauzan
Published: (2009)