Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application
This paper presents a numerical simulation to examine the electrical performance of a Junctionless Gate-All-Around (JGAA) Field Effect Transistor (FET) as an inverter. The advantages of the device offer smaller threshold voltage, lower leakage current, better electrostatic control, better device per...
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my.utm.978252022-11-02T09:51:47Z http://eprints.utm.my/id/eprint/97825/ Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application Ho, Kok Pow N., Mathan Mohamed Ali, Mohamed Sultan Mohd. Napi, Muhammad Luqman Hosseingholipouras, Ali Abd. Hamid, Fatimah Khairiah TK Electrical engineering. Electronics Nuclear engineering This paper presents a numerical simulation to examine the electrical performance of a Junctionless Gate-All-Around (JGAA) Field Effect Transistor (FET) as an inverter. The advantages of the device offer smaller threshold voltage, lower leakage current, better electrostatic control, better device performance and can operate at a high speed. Thus, to examine the potential of the device for an inverter application, the characterization of the Junctionless GAA MOSFET is performed to identify the critical device parameters in optimizing the device performance. Besides, the optimization of the device is aimed to be used to meet IRDS standard, particularly for a low power application. The characterization of electrical properties conducted based on carrier concentration, radius, gate length and drain voltage. It is found that the drain voltage and gate length give a significant impact on the threshold voltage and on-state current of the Junctionless GAA MOSFET but the minimum impact on its leakage current. However, the device parameters such as carrier concentration and radius of the channel contributed significant impact on the threshold voltage, on-state current and leakage current. The simulated result of the optimized device for N-MOS and P-MOS indicates that its electrical properties enhanced significantly. For N-MOS, the threshold voltage, current-ratio and subthreshold and drain induced barrier lowering were calculated as 0.350V, 1.606, 60 mV and 40.04 mV/dec, respectively, meanwhile for P-MOS, the threshold voltage, current-ratio and subthreshold and drain induced barrier lowering were obtained as 0.355V, 4.132, 60 mV and 60.6 mV/dec, accordingly. These results revealed that the Junctionless GAA MOSFET could meet the requirement set by IRDS for a low power application which can offer minimum leakage current and suitable to be used for an inverter application. Penerbit UTM Press 2021-09-15 Article PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/97825/1/FatimahKhairiah2021_ElectricalCharacterizationofNMOSandPMOS.pdf Ho, Kok Pow and N., Mathan and Mohamed Ali, Mohamed Sultan and Mohd. Napi, Muhammad Luqman and Hosseingholipouras, Ali and Abd. Hamid, Fatimah Khairiah (2021) Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application. ELEKTRIKA- Journal of Electrical Engineering, 20 (2-2). pp. 93-97. ISSN 0128-4428 https://elektrika.utm.my/index.php/ELEKTRIKA_Journal/article/view/276 NA |
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TK Electrical engineering. Electronics Nuclear engineering Ho, Kok Pow N., Mathan Mohamed Ali, Mohamed Sultan Mohd. Napi, Muhammad Luqman Hosseingholipouras, Ali Abd. Hamid, Fatimah Khairiah Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application |
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This paper presents a numerical simulation to examine the electrical performance of a Junctionless Gate-All-Around (JGAA) Field Effect Transistor (FET) as an inverter. The advantages of the device offer smaller threshold voltage, lower leakage current, better electrostatic control, better device performance and can operate at a high speed. Thus, to examine the potential of the device for an inverter application, the characterization of the Junctionless GAA MOSFET is performed to identify the critical device parameters in optimizing the device performance. Besides, the optimization of the device is aimed to be used to meet IRDS standard, particularly for a low power application. The characterization of electrical properties conducted based on carrier concentration, radius, gate length and drain voltage. It is found that the drain voltage and gate length give a significant impact on the threshold voltage and on-state current of the Junctionless GAA MOSFET but the minimum impact on its leakage current. However, the device parameters such as carrier concentration and radius of the channel contributed significant impact on the threshold voltage, on-state current and leakage current. The simulated result of the optimized device for N-MOS and P-MOS indicates that its electrical properties enhanced significantly. For N-MOS, the threshold voltage, current-ratio and subthreshold and drain induced barrier lowering were calculated as 0.350V, 1.606, 60 mV and 40.04 mV/dec, respectively, meanwhile for P-MOS, the threshold voltage, current-ratio and subthreshold and drain induced barrier lowering were obtained as 0.355V, 4.132, 60 mV and 60.6 mV/dec, accordingly. These results revealed that the Junctionless GAA MOSFET could meet the requirement set by IRDS for a low power application which can offer minimum leakage current and suitable to be used for an inverter application. |
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Article |
author |
Ho, Kok Pow N., Mathan Mohamed Ali, Mohamed Sultan Mohd. Napi, Muhammad Luqman Hosseingholipouras, Ali Abd. Hamid, Fatimah Khairiah |
author_facet |
Ho, Kok Pow N., Mathan Mohamed Ali, Mohamed Sultan Mohd. Napi, Muhammad Luqman Hosseingholipouras, Ali Abd. Hamid, Fatimah Khairiah |
author_sort |
Ho, Kok Pow |
title |
Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application |
title_short |
Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application |
title_full |
Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application |
title_fullStr |
Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application |
title_full_unstemmed |
Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application |
title_sort |
electrical characterization of n-mos and p-mos junctionless gate-all-around (gaa) mosfet for an inverter application |
publisher |
Penerbit UTM Press |
publishDate |
2021 |
url |
http://eprints.utm.my/id/eprint/97825/1/FatimahKhairiah2021_ElectricalCharacterizationofNMOSandPMOS.pdf http://eprints.utm.my/id/eprint/97825/ https://elektrika.utm.my/index.php/ELEKTRIKA_Journal/article/view/276 |
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1748703150162837504 |
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13.160551 |