Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application

• Main Authors: Ho, Kok Pow, N., Mathan, Mohamed Ali, Mohamed Sultan, Mohd. Napi, Muhammad Luqman, Hosseingholipouras, Ali, Abd. Hamid, Fatimah Khairiah
• Format: Article
• Language: English
• Published: Penerbit UTM Press 2021
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/97825/1/FatimahKhairiah2021_ElectricalCharacterizationofNMOSandPMOS.pdf; http://eprints.utm.my/id/eprint/97825/; https://elektrika.utm.my/index.php/ELEKTRIKA_Journal/article/view/276

This paper presents a numerical simulation to examine the electrical performance of a Junctionless Gate-All-Around (JGAA) Field Effect Transistor (FET) as an inverter. The advantages of the device offer smaller threshold voltage, lower leakage current, better electrostatic control, better device performance and can operate at a high speed. Thus, to examine the potential of the device for an inverter application, the characterization of the Junctionless GAA MOSFET is performed to identify the critical device parameters in optimizing the device performance. Besides, the optimization of the device is aimed to be used to meet IRDS standard, particularly for a low power application. The characterization of electrical properties conducted based on carrier concentration, radius, gate length and drain voltage. It is found that the drain voltage and gate length give a significant impact on the threshold voltage and on-state current of the Junctionless GAA MOSFET but the minimum impact on its leakage current. However, the device parameters such as carrier concentration and radius of the channel contributed significant impact on the threshold voltage, on-state current and leakage current. The simulated result of the optimized device for N-MOS and P-MOS indicates that its electrical properties enhanced significantly. For N-MOS, the threshold voltage, current-ratio and subthreshold and drain induced barrier lowering were calculated as 0.350V, 1.606, 60 mV and 40.04 mV/dec, respectively, meanwhile for P-MOS, the threshold voltage, current-ratio and subthreshold and drain induced barrier lowering were obtained as 0.355V, 4.132, 60 mV and 60.6 mV/dec, accordingly. These results revealed that the Junctionless GAA MOSFET could meet the requirement set by IRDS for a low power application which can offer minimum leakage current and suitable to be used for an inverter application.