A Case Study for Reliability-Aware in SoC Analog Circuit Design
This paper provides a working knowledge of Negative Bias Temperature Instability (NBTI) awareness to the circuit design community for reliable design of the System-Ona-Chip (SoC) analog circuit. The reliability performance of all matched pair circuits, such as Bandgap Reference, is at the mercy of...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/4804/1/A_Case_Study_for_Reliability-Aware_in_SoC_Analog_final.pdf http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5716255 http://eprints.utp.edu.my/4804/ |
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