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s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model

Buffer insertion and wire sizing have been proven effective in solving the timing optimization problem in VLSI interconnect design. In this paper, we describe a graph-based maze interconnect routing algorithm for VLSI designs. An interconnect routing and buffer insertion with look-ahead algorithm is...

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書目詳細資料
Main Authors:	Md. Yusof, Zulkifli, Khalil Hani, M., Marsono, M. N.
格式:	Conference or Workshop Item
出版:	2012
在線閱讀:	http://eprints.utm.my/id/eprint/34199/
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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