An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts

• Main Authors: Uttraphan, C., Shaikh Husin, N., Khalil Hani, M.
• Format: Article
• Published: Turkiye Klinikleri Journal of Medical Sciences 2017
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/75603/; https://www.scopus.com/inward/record.uri?eid=2-s2.0-85017360985&doi=10.3906%2felk-1411-129&partnerID=40&md5=7852249b1029ec7a1a1125e044158c9f

We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI layout designs. The algorithm is designed to handle multiconstraint optimizations, namely timing performance and power dissipation. The proposed algorithm is called HRTB-LA, which stands for hybrid rout...