Hybrid routing tree with buffer insertion under obstacle constraints
Performance optimization in very-large-scale integration (VLSI) design is the key success in today's design automation methodologies. One of the performance issues is the interconnect delay in deep sub-micron VLSI circuits. The interconnect delay becomes more dominant compared to gate delay whe...
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| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/59309/ http://dx.doi.org/10.1109/SCOReD.2013.7002621 |
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