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s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model

Buffer insertion and wire sizing have been proven effective in solving the timing optimization problem in VLSI interconnect design. In this paper, we describe a graph-based maze interconnect routing algorithm for VLSI designs. An interconnect routing and buffer insertion with look-ahead algorithm is...

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Main Authors: Md. Yusof, Zulkifli, Khalil Hani, M., Marsono, M. N.
Format: Conference or Workshop Item
Published: 2012
Online Access:http://eprints.utm.my/id/eprint/34199/
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spelling my.utm.341992017-09-10T06:07:02Z http://eprints.utm.my/id/eprint/34199/ s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model Md. Yusof, Zulkifli Khalil Hani, M. Marsono, M. N. Buffer insertion and wire sizing have been proven effective in solving the timing optimization problem in VLSI interconnect design. In this paper, we describe a graph-based maze interconnect routing algorithm for VLSI designs. An interconnect routing and buffer insertion with look-ahead algorithm is used to construct a maze routing path. Simultaneous routing with buffer insertion and wire sizing is applied, taking into account wire and buffer obstacles. An iterative RLC interconnect model is proposed to estimate interconnect delay. Experimental results proves the effectiveness of the look-ahead scheme and shows RLC delay model improvement in delay estimation. 2012 Conference or Workshop Item PeerReviewed Md. Yusof, Zulkifli and Khalil Hani, M. and Marsono, M. N. (2012) s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model. In: 2012 IEEE International Conference on Circuits and Systems (ICCAS 2012).
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
description Buffer insertion and wire sizing have been proven effective in solving the timing optimization problem in VLSI interconnect design. In this paper, we describe a graph-based maze interconnect routing algorithm for VLSI designs. An interconnect routing and buffer insertion with look-ahead algorithm is used to construct a maze routing path. Simultaneous routing with buffer insertion and wire sizing is applied, taking into account wire and buffer obstacles. An iterative RLC interconnect model is proposed to estimate interconnect delay. Experimental results proves the effectiveness of the look-ahead scheme and shows RLC delay model improvement in delay estimation.
format Conference or Workshop Item
author Md. Yusof, Zulkifli
Khalil Hani, M.
Marsono, M. N.
spellingShingle Md. Yusof, Zulkifli
Khalil Hani, M.
Marsono, M. N.
s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model
author_facet Md. Yusof, Zulkifli
Khalil Hani, M.
Marsono, M. N.
author_sort Md. Yusof, Zulkifli
title s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model
title_short s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model
title_full s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model
title_fullStr s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model
title_full_unstemmed s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model
title_sort s.rabila2: an optimal vlsi routing algorithm with buffer insertion using iterative rlc model
publishDate 2012
url http://eprints.utm.my/id/eprint/34199/
_version_ 1643649535509004288
score 13.211869

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