The study of the effect of MOS transistor scaling on the critical device parameters
Since the invention of transistors some 30 years ago, CMOS devices have been scale down aggressively in each technology generations to achieve higher integration density and performance. The device shrinkage allow denser circuits, more functions per floor space, more complicated and integrated desig...
Saved in:
Main Author: | Zazurina Abd Rahman |
---|---|
Other Authors: | Ramzan Mat Ayub (Advisor) |
Format: | Learning Object |
Language: | English |
Published: |
Universiti Malaysia Perlis
2008
|
Subjects: | |
Online Access: | http://dspace.unimap.edu.my/xmlui/handle/123456789/2342 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Fabrication Of 50 µm transistor and AlNiAu interconnection process
by: Shaffie Husin
Published: (2008) -
Electrical characterization of 0.15µm CMOS Transistor using TSUPREM-4 and MEDICI
by: Low Pooi Lam
Published: (2008) -
Electrical characterization of 0.13 µm NMOS transistor with Retrograde Well and Halo Implant Structure Respectively
by: Anas Redzuan, Mokhtar
Published: (2008) -
Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities
by: Izny Atikah Ahmad Fahmi
Published: (2008) -
The effect of Phosphorous implant in converting the Enhancement Mode Transistor into Depletion Mode Transistor
by: Hazian, Mamat
Published: (2008)