Coherent effect on LOCOS and STI technique for 0.18 µm CMOS technology using Taurus Workbench

• 第一著者: Wan Shafie Wan Sulaiman
• その他の著者: Ruslinda A. Rahim (Advisor)
• フォーマット: Learning Object
• 言語: English
• 出版事項: Universiti Malaysia Perlis 2008
• 主題: Integrated circuits > Very large scale integration; Local oxidation of silicon (LOCOS); Shallow Trench Isolation (STI); Transistors; CMOS transistors; Metal oxide semiconductors, Complementary; Integrated circuits
• オンライン･アクセス: http://dspace.unimap.edu.my/xmlui/handle/123456789/1955

LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation) are two isolation techniques used in integrated circuit fabrication. Further device scaling using LOCOS technique is no longer practical for technology generations below 0.35 µm. STI technique was thus introduced because of its...