Design of a 5GHz phase-locked loop

• Main Authors: Mohamad Ashari, Zainab, Nordin, Anis Nurashikin, Ibrahimy, Muhammad Ibn
• Format: Conference or Workshop Item
• Language: English
• Published: 2011
• Subjects: TK7885 Computer engineering
• Online Access: http://irep.iium.edu.my/15122/1/06088316.pdf; http://irep.iium.edu.my/15122/; http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6086117

Noise or jitter performance is a major concern in the design of phase-locked loop (PLL). Linearity and speed issues are of relevance when receiving data at gigahertz speed. The main function of a PLL circuit is to generate stable higher frequencies (GHz) output from a lower input frequency signal. P...