Design of a 5GHz phase-locked loop

• Main Authors: Mohamad Ashari, Zainab, Nordin, Anis Nurashikin, Ibrahimy, Muhammad Ibn
• Format: Conference or Workshop Item
• Language: English
• Published: 2011
• Subjects: TK7885 Computer engineering
• Online Access: http://irep.iium.edu.my/15122/1/06088316.pdf; http://irep.iium.edu.my/15122/; http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6086117

Noise or jitter performance is a major concern in the design of phase-locked loop (PLL). Linearity and speed issues are of relevance when receiving data at gigahertz speed. The main function of a PLL circuit is to generate stable higher frequencies (GHz) output from a lower input frequency signal. PLLs are often used in communication technology to implement a variety of functions such as clock recovery, frequency multiplication, and clock synchronization. This paper presents the design and simulation results of PLL with low jitter performance. The key goal is to design and develop an analog PLL circuit for 5 GHz clock data recovery circuit. The PLL comprises of a phase frequency detector (PFD), low pass filter, voltage controlled oscillator (VCO), and feedback divider. In this work, analog mixed-signal architecture of PLL is simulated using hardware discipline modeling language, Verilog-AMS HDL. Multilingual and Mixed-Signal simulator SMASH software has been used for the Verilog-AMS design. A 5 GHz PLL with less jitter was successfully designed in this work.