A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree

• Main Authors: Rahim At Samsuddin, H. A., Ab. Rahman, A. A. H., Andaljayalakshmi, G., Ahmad, R. B.
• Format: Conference or Workshop Item
• Published: Faculty of Electrical Engineering 2008
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/9961/; http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:127756

This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization of macro-cell layout in very large scaled integrated (VLSI) design. Three...