Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs

• Main Authors: Hoo, C.S., Kanesan, J., Ramiah, H.
• Format: Article
• Published: John Wiley & Sons 2015
• Subjects: T Technology (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.um.edu.my/13947/; http://onlinelibrary.wiley.com/doi/10.1002/cta.1939/abstract

From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggre...