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Asymmetrical nine-level inverter topology with reduce power semicondutor devices

In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging available switches and dc sources in a fashion such that the maximum combination of addition and...

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書誌詳細
主要な著者:	Arif, M. S., Ayob, S. M., Salam, Z.
フォーマット:	論文
言語:	English
出版事項:	Universitas Ahmad Dahlan 2018
主題:	TK Electrical engineering. Electronics Nuclear engineering
オンライン･アクセス:	http://eprints.utm.my/id/eprint/79807/1/MSaadArif2018_AsymmetricalNineLevelInverterTopology.pdf http://eprints.utm.my/id/eprint/79807/ http://dx.doi.org/10.12928/TELKOMNIKA.v16i1.8520
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