Asymmetrical nine-level inverter topology with reduce power semicondutor devices
In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging available switches and dc sources in a fashion such that the maximum combination of addition and...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Universitas Ahmad Dahlan
2018
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/79807/1/MSaadArif2018_AsymmetricalNineLevelInverterTopology.pdf http://eprints.utm.my/id/eprint/79807/ http://dx.doi.org/10.12928/TELKOMNIKA.v16i1.8520 |
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| Summary: | In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging available switches and dc sources in a fashion such that the maximum combination of addition and subtraction of the input dc sources can be obtained. To verify the viability of the proposed topology, the circuit model is developed and simulated in Matlab-Simulink software. Experimental testing results of the proposed nine-level inverter topology, developed in the laboratory, are presented. A low frequency switching strategy is employed in this work. The results show that the proposed topology is capable to produce a nine-level output voltage, capable in handling inductive load and yields acceptable harmonic distortion content. |
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