Implementation and analysis of a 15-Level inverter topology With reduced switch count
Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been p...
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Main Authors: | , , , , |
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Format: | Article |
Published: |
Institute of Electrical and Electronics Engineers
2021
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Subjects: | |
Online Access: | http://eprints.um.edu.my/27955/ |
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