Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects
Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level archi...
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my.utm.526902018-06-29T23:04:47Z http://eprints.utm.my/id/eprint/52690/ Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects Chin, Huei Chaeng Lim, Cheng Siong Wong, Weng Soon Danapalasingam, Kumeresan A. Arora, Vijay K. Tan, Michael Loong Peng TK Electrical engineering. Electronics Nuclear engineering Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (- and -), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances. Hindawi Publishing Corporation 2014 Article PeerReviewed Chin, Huei Chaeng and Lim, Cheng Siong and Wong, Weng Soon and Danapalasingam, Kumeresan A. and Arora, Vijay K. and Tan, Michael Loong Peng (2014) Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects. Journal of Nanomaterials . pp. 1-14. ISSN 1687-4110 http://dx.doi.org/10.1155/2014/879813 DOI:10.1155/2014/879813 |
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TK Electrical engineering. Electronics Nuclear engineering Chin, Huei Chaeng Lim, Cheng Siong Wong, Weng Soon Danapalasingam, Kumeresan A. Arora, Vijay K. Tan, Michael Loong Peng Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects |
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Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (- and -), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances. |
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Article |
author |
Chin, Huei Chaeng Lim, Cheng Siong Wong, Weng Soon Danapalasingam, Kumeresan A. Arora, Vijay K. Tan, Michael Loong Peng |
author_facet |
Chin, Huei Chaeng Lim, Cheng Siong Wong, Weng Soon Danapalasingam, Kumeresan A. Arora, Vijay K. Tan, Michael Loong Peng |
author_sort |
Chin, Huei Chaeng |
title |
Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects |
title_short |
Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects |
title_full |
Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects |
title_fullStr |
Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects |
title_full_unstemmed |
Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects |
title_sort |
enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-mosfet with interconnects |
publisher |
Hindawi Publishing Corporation |
publishDate |
2014 |
url |
http://eprints.utm.my/id/eprint/52690/ http://dx.doi.org/10.1155/2014/879813 |
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