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Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor

Numerical analysis of vertical double-gate MOSFETs (VDGM) that incorporates dielectric-pocket (DP) is addressed in this paper for the suppression of short-channel effects (SCE) and bulk punch-through. The comparison between standard and VDGM-DP revealed the advantages of DP for inhibition of SCE. Th...

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Main Authors: Saad, Ismail, Lee, Razak M. A., Munawar, A. R., Ahmadi, M. Taghi, Ismail, Razali
Format: Book Section
Published: American Institute of Physics 2009
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/13017/
http://dx.doi.org/10.1063/1.3160269
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spelling my.utm.130172011-07-13T02:14:04Z http://eprints.utm.my/id/eprint/13017/ Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor Saad, Ismail Lee, Razak M. A. Munawar, A. R. Ahmadi, M. Taghi Ismail, Razali TK Electrical engineering. Electronics Nuclear engineering Numerical analysis of vertical double-gate MOSFETs (VDGM) that incorporates dielectric-pocket (DP) is addressed in this paper for the suppression of short-channel effects (SCE) and bulk punch-through. The comparison between standard and VDGM-DP revealed the advantages of DP for inhibition of SCE. The transfer and output characteristics of the VDGM-DP indicates a reasonable value of threshold voltage (V(T)), drive and off -leakage current (ION and I(OFF)), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The DP incorporated on top of transistor turret is revealed to increase the saturation current I(Dsat) due to drain-end electric field reduction that improved the carrier mobility and the drain current tremendously. American Institute of Physics 2009 Book Section PeerReviewed Saad, Ismail and Lee, Razak M. A. and Munawar, A. R. and Ahmadi, M. Taghi and Ismail, Razali (2009) Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor. In: Nanoscience And Nanotechnology. AIP Conference Proceedings, 1136 . American Institute of Physics, USA, 840 -844. ISBN 978-0-7354-0673-5 http://dx.doi.org/10.1063/1.3160269 doi:10.1063/1.3160269
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Saad, Ismail
Lee, Razak M. A.
Munawar, A. R.
Ahmadi, M. Taghi
Ismail, Razali
Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor
description Numerical analysis of vertical double-gate MOSFETs (VDGM) that incorporates dielectric-pocket (DP) is addressed in this paper for the suppression of short-channel effects (SCE) and bulk punch-through. The comparison between standard and VDGM-DP revealed the advantages of DP for inhibition of SCE. The transfer and output characteristics of the VDGM-DP indicates a reasonable value of threshold voltage (V(T)), drive and off -leakage current (ION and I(OFF)), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The DP incorporated on top of transistor turret is revealed to increase the saturation current I(Dsat) due to drain-end electric field reduction that improved the carrier mobility and the drain current tremendously.
format Book Section
author Saad, Ismail
Lee, Razak M. A.
Munawar, A. R.
Ahmadi, M. Taghi
Ismail, Razali
author_facet Saad, Ismail
Lee, Razak M. A.
Munawar, A. R.
Ahmadi, M. Taghi
Ismail, Razali
author_sort Saad, Ismail
title Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor
title_short Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor
title_full Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor
title_fullStr Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor
title_full_unstemmed Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor
title_sort numerical analysis of vertical double gate mosfets (vdgm) with dielectric pocket (dp) effects on silicon pillar for nanoscale transistor
publisher American Institute of Physics
publishDate 2009
url http://eprints.utm.my/id/eprint/13017/
http://dx.doi.org/10.1063/1.3160269
_version_ 1643646095476129792
score 13.160551

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