A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs
A Design-for-test (DfT) technique is proposed in this paper for a test method, by which detecting open defects occurring interconnects between 3D stacked SRAM IC and a printed circuit board and among dies inside them. The test method is based on the supply current that is made flow through an...
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| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2023
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| Online Access: | http://eprints.utem.edu.my/id/eprint/28088/1/A%20DfT%20technique%20for%20electrical%20interconnect%20testing%20of%20circuit%20boards%20with%203D%20Stacked%20SRAM%20ICs.pdf http://eprints.utem.edu.my/id/eprint/28088/ https://ieeexplore.ieee.org/document/10339543 |
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