Holdings: A study of proper integrated circuit (IC) layout techniques for a parallel adder

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Bibliographic Details
Main Author:	Kau, Zee Shuang
Other Authors:	Norina Idris
Format:	Learning Object
Language:	English
Published:	Universiti Malaysia Perlis (UniMAP) 2015
Subjects:	Integrated Circuit (IC) Parallel adder CMOS technology Parallel adder > Design and construction
Online Access:	http://dspace.unimap.edu.my:80/xmlui/handle/123456789/40274
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