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A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs

A Design-for-test (DfT) technique is proposed in this paper for a test method, by which detecting open defects occurring interconnects between 3D stacked SRAM IC and a printed circuit board and among dies inside them. The test method is based on the supply current that is made flow through an...

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Main Authors: Ikiri, Yuki, Yotsuyanagi, Hiroyuki, Ali, Fara Ashikin, Lu, Shyue-Kung, Hashizume, Masaki
Format: Conference or Workshop Item
Language:English
Published: 2023
Online Access:http://eprints.utem.edu.my/id/eprint/28088/1/A%20DfT%20technique%20for%20electrical%20interconnect%20testing%20of%20circuit%20boards%20with%203D%20Stacked%20SRAM%20ICs.pdf
http://eprints.utem.edu.my/id/eprint/28088/
https://ieeexplore.ieee.org/document/10339543
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spelling my.utem.eprints.280882024-10-17T16:19:09Z http://eprints.utem.edu.my/id/eprint/28088/ A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs Ikiri, Yuki Yotsuyanagi, Hiroyuki Ali, Fara Ashikin Lu, Shyue-Kung Hashizume, Masaki A Design-for-test (DfT) technique is proposed in this paper for a test method, by which detecting open defects occurring interconnects between 3D stacked SRAM IC and a printed circuit board and among dies inside them. The test method is based on the supply current that is made flow through an interconnect to be tested. The DfT technique utilizes a built- in current sensor circuit to detect the open defects. It is shown that open defects occurring at interconnects among dies designed by the DfT method in a 3D stacked SRAM IC, and between the IC and a circuit board can be detected by the supply current test method. 2023 Conference or Workshop Item PeerReviewed text en http://eprints.utem.edu.my/id/eprint/28088/1/A%20DfT%20technique%20for%20electrical%20interconnect%20testing%20of%20circuit%20boards%20with%203D%20Stacked%20SRAM%20ICs.pdf Ikiri, Yuki and Yotsuyanagi, Hiroyuki and Ali, Fara Ashikin and Lu, Shyue-Kung and Hashizume, Masaki (2023) A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs. In: 12th IEEE CPMT Symposium Japan, ICSJ 2023, 15 November 2023 through 17 November 2023, Kyoto. https://ieeexplore.ieee.org/document/10339543
institution Universiti Teknikal Malaysia Melaka
building UTEM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknikal Malaysia Melaka
content_source UTEM Institutional Repository
url_provider http://eprints.utem.edu.my/
language English
description A Design-for-test (DfT) technique is proposed in this paper for a test method, by which detecting open defects occurring interconnects between 3D stacked SRAM IC and a printed circuit board and among dies inside them. The test method is based on the supply current that is made flow through an interconnect to be tested. The DfT technique utilizes a built- in current sensor circuit to detect the open defects. It is shown that open defects occurring at interconnects among dies designed by the DfT method in a 3D stacked SRAM IC, and between the IC and a circuit board can be detected by the supply current test method.
format Conference or Workshop Item
author Ikiri, Yuki
Yotsuyanagi, Hiroyuki
Ali, Fara Ashikin
Lu, Shyue-Kung
Hashizume, Masaki
spellingShingle Ikiri, Yuki
Yotsuyanagi, Hiroyuki
Ali, Fara Ashikin
Lu, Shyue-Kung
Hashizume, Masaki
A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs
author_facet Ikiri, Yuki
Yotsuyanagi, Hiroyuki
Ali, Fara Ashikin
Lu, Shyue-Kung
Hashizume, Masaki
author_sort Ikiri, Yuki
title A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs
title_short A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs
title_full A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs
title_fullStr A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs
title_full_unstemmed A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs
title_sort dft technique for electrical interconnect testing of circuit boards with 3d stacked sram ics
publishDate 2023
url http://eprints.utem.edu.my/id/eprint/28088/1/A%20DfT%20technique%20for%20electrical%20interconnect%20testing%20of%20circuit%20boards%20with%203D%20Stacked%20SRAM%20ICs.pdf
http://eprints.utem.edu.my/id/eprint/28088/
https://ieeexplore.ieee.org/document/10339543
_version_ 1814061459792986112
score 13.214268

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