Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

• 主要な著者: Elgomati, H.A., Majlis, B.Y., Ahmad, I., Salehuddin, F., Hamid, F.A., Zaharim, A., Mohamad, T.Z., Apte, P.R.
• フォーマット: 論文
• 出版事項: 2017
• オンライン･アクセス: http://dspace.uniten.edu.my:80/jspui/handle/123456789/5240

This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process param...