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Statistical process modelling for 32nm high-K/metal gate PMOS device

The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric...

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Main Authors: Maheran, A.H.A., Noor Faizah, Z.A., Menon, P.S., Ahmad, I., Apte, P.R., Kalaivani, T., Salehuddin, F.
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Published: 2017
Online Access:http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5212
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spelling my.uniten.dspace-52122017-11-15T02:56:39Z Statistical process modelling for 32nm high-K/metal gate PMOS device Maheran, A.H.A. Noor Faizah, Z.A. Menon, P.S. Ahmad, I. Apte, P.R. Kalaivani, T. Salehuddin, F. The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction. © 2014 IEEE. 2017-11-15T02:56:39Z 2017-11-15T02:56:39Z 2014 http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5212
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction. © 2014 IEEE.
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author Maheran, A.H.A.
Noor Faizah, Z.A.
Menon, P.S.
Ahmad, I.
Apte, P.R.
Kalaivani, T.
Salehuddin, F.
spellingShingle Maheran, A.H.A.
Noor Faizah, Z.A.
Menon, P.S.
Ahmad, I.
Apte, P.R.
Kalaivani, T.
Salehuddin, F.
Statistical process modelling for 32nm high-K/metal gate PMOS device
author_facet Maheran, A.H.A.
Noor Faizah, Z.A.
Menon, P.S.
Ahmad, I.
Apte, P.R.
Kalaivani, T.
Salehuddin, F.
author_sort Maheran, A.H.A.
title Statistical process modelling for 32nm high-K/metal gate PMOS device
title_short Statistical process modelling for 32nm high-K/metal gate PMOS device
title_full Statistical process modelling for 32nm high-K/metal gate PMOS device
title_fullStr Statistical process modelling for 32nm high-K/metal gate PMOS device
title_full_unstemmed Statistical process modelling for 32nm high-K/metal gate PMOS device
title_sort statistical process modelling for 32nm high-k/metal gate pmos device
publishDate 2017
url http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5212
_version_ 1644493616549199872
score 13.222552

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