Statistical process modelling for 32nm high-K/metal gate PMOS device
The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric...
Saved in:
| Main Authors: | , , , , , , |
|---|---|
| Format: | |
| Published: |
2017
|
| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5212 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|