Statistical process modelling for 32nm high-K/metal gate PMOS device

• 主要な著者: Maheran, A.H.A., Noor Faizah, Z.A., Menon, P.S., Ahmad, I., Apte, P.R., Kalaivani, T., Salehuddin, F.
• 出版事項: 2017
• オンライン･アクセス: http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5212

The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric...