Statistical process modelling for 32nm high-K/metal gate PMOS device

• المؤلفون الرئيسيون: Maheran, A.H.A., Noor Faizah, Z.A., Menon, P.S., Ahmad, I., Apte, P.R., Kalaivani, T., Salehuddin, F.
• منشور في: 2017
• الوصول للمادة أونلاين: http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5212

The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction. © 2014 IEEE.