Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

• Main Authors: Elgomati H.A., Majlis B.Y., Ahmad I., Salehuddin F., Hamid F.A., Zaharim A., Mohamad T.Z., Apte P.R.
• Other Authors: 36536722700
• Format: Article
• Published: 2023
• Subjects: 32 nm PMOS device; Compensation implantation; HALO; S/D implantation; Taguchi's method; Threshold voltage

This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process param...