Modelling of process parameters for 32nm PMOS transistor using Taguchi method

• Main Authors: Elgomati H.A., Majlis B.Y., Hamid A.M.A., Susthitha P.M., Ahmad I.
• Other Authors: 36536722700
• Format: Conference paper
• Published: 2023
• Subjects: 32nm PMOS; ANOM; ANOVA; compensation implantations; L18 orthogonal array; Taguchi Method; Threshold voltage; Analysis of variance (ANOVA); CMOS integrated circuits; Computer simulation; Taguchi methods; Analysis of means; Circuit performance; CMOS technology; Device parameters; Electrical characterization; Fabrication tool; Mean values; Modelling of process; Nanometer level; Noise factor; Objective functions; pMOS transistors; Process noise; Process parameters; Robust designs; S/N ratio; Taguchi; Mathematical models

As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transistor. Using Taguchi's experimental robust design strategy seven process parameters were assigned to 7 columns of the L18 orthogonal array to conduct 18 simulation runs. Fabrication of the 32nm PMOS transistor was simulated by using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. These simulators were used for computing Vth simulations for each row of the L18 array with 4 combinations of the 2 noise factors. Taguchi's nominal-the-best S/N ratio was used as the objective functions for the minimization of variance in Vth. The best settings of process parameters were determined using Analysis of Mean (ANOM) and Analysis of Variance (ANOVA) for reducing the variability of Vth. The best settings were used for verification simulations and the results showed that the Vth values had the least variance and the mean value could be adjusted to-0.103V +-0.003 for PMOS, which is well within ITRS specifications. � 2012 IEEE.