Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling
This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of t...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Institute of Advanced Engineering and Science (IAES)
2021
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| Subjects: | |
| Online Access: | http://umpir.ump.edu.my/id/eprint/30151/1/GAA%20TFET.pdf http://umpir.ump.edu.my/id/eprint/30151/ http://doi.org/10.11591/ijece.v11i1.pp780-787 http://doi.org/10.11591/ijece.v11i1.pp780-787 |
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| Summary: | This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics. |
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