Cover Image

Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing

Saved in:
Bibliographic Details
Main Author: Yap, Wei Cheng
Format: Final Year Project
Published: 2024
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://utpedia.utp.edu.my/id/eprint/28665/
Tags: Add Tag
No Tags, Be the first to tag this record!
id oai:utpedia.utp.edu.my:28665
record_format eprints
spelling oai:utpedia.utp.edu.my:286652024-08-08T09:35:11Z http://utpedia.utp.edu.my/id/eprint/28665/ Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing Yap, Wei Cheng TK Electrical engineering. Electronics Nuclear engineering 2024-05 Final Year Project NonPeerReviewed Yap, Wei Cheng (2024) Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing. [Final Year Project] (Submitted)
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Electronic and Digitized Intellectual Asset
url_provider http://utpedia.utp.edu.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Yap, Wei Cheng
Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing
format Final Year Project
author Yap, Wei Cheng
author_facet Yap, Wei Cheng
author_sort Yap, Wei Cheng
title Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing
title_short Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing
title_full Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing
title_fullStr Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing
title_full_unstemmed Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing
title_sort synthesis and fpga hardware simulation of an open-source risc-v core for edge computing
publishDate 2024
url http://utpedia.utp.edu.my/id/eprint/28665/
_version_ 1807051986803097600
score 13.214268

Similar Items