Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing
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oai:utpedia.utp.edu.my:286652024-08-08T09:35:11Z http://utpedia.utp.edu.my/id/eprint/28665/ Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing Yap, Wei Cheng TK Electrical engineering. Electronics Nuclear engineering 2024-05 Final Year Project NonPeerReviewed Yap, Wei Cheng (2024) Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing. [Final Year Project] (Submitted) |
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TK Electrical engineering. Electronics Nuclear engineering Yap, Wei Cheng Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing |
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Final Year Project |
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Yap, Wei Cheng |
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Yap, Wei Cheng |
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Yap, Wei Cheng |
title |
Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing |
title_short |
Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing |
title_full |
Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing |
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Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing |
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Synthesis and FPGA hardware simulation of an open-source RISC-V core for edge computing |
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synthesis and fpga hardware simulation of an open-source risc-v core for edge computing |
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2024 |
url |
http://utpedia.utp.edu.my/id/eprint/28665/ |
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1807051986803097600 |
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13.209306 |