An AES tightly coupled hardware accelerator in an FPGA-based Embedded processor core

• Main Authors: Hani, Mohamed Khalil, Vishnu, P. Nambiar, Arif, Irwansyah
• Format: Book Section
• Published: IEEE Explore 2009
• Subjects: TA Engineering (General). Civil engineering (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/12962/; http://dx.doi.org/10.1109/ICCET.2009.248

This paper presents the implementation of a tightly coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate Advanced Encryption Standard (AES) operations in 128, 192 and 256-bits, for application in a high-performance embedded system...