Joint and marginal probability analyses of Markov Random Field networks for digital logic circuits
With the device scaling up to nano-level, the integrated circuits are expected to face high computing error rates. This increased rate is the outcome of random and dynamic noise injected in the circuit which becomes more vulnerable due to low supply voltages and extremely small transistor dimensions...
Saved in:
Main Authors: | Anwer, Jahanzeb, Khalid, Usman, Singh, Narinderjit, Hamid, Nor H., Asirvadam, Vijanth S. |
---|---|
格式: | Conference or Workshop Item |
出版: |
2010
|
主題: | |
在線閱讀: | http://eprints.utp.edu.my/4639/1/JointMarMarkovCircuit.pdf http://eprints.utp.edu.my/4639/ |
標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
相似書籍
-
ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE
FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN
由: ANWER, JAHANZEB ANWER
出版: (2011) -
Highly noise-tolerant design of digital logic gates using Markov Random Field modelling
由: Anwer, Janhanzeb, et al.
出版: (2010) -
Highly noise-tolerant design of digital logic gates using Markov Random Field modelling
由: Anwer, Janhanzeb, et al.
出版: (2010) -
An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs
Zoom
See larger image (with zoom)
Share your own customer images
Publisher: learn how customers can search inside this book.
An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs
由: Anwer, Janhanzeb, et al.
出版: (2011) -
A novel error-detection mechanism for digital circuits using Markov random field modelling
出版: (2012)