Joint and marginal probability analyses of Markov Random Field networks for digital logic circuits

With the device scaling up to nano-level, the integrated circuits are expected to face high computing error rates. This increased rate is the outcome of random and dynamic noise injected in the circuit which becomes more vulnerable due to low supply voltages and extremely small transistor dimensions...

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Main Authors: Anwer, Jahanzeb, Khalid, Usman, Singh, Narinderjit, Hamid, Nor H., Asirvadam, Vijanth S.
格式: Conference or Workshop Item
出版: 2010
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在線閱讀:http://eprints.utp.edu.my/4639/1/JointMarMarkovCircuit.pdf
http://eprints.utp.edu.my/4639/
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