Probability Formulation of Soft Error in Memory Circuit
Downscaling threatens the designers invested in integrity and error mitigation against soft errors. This study formulated the probability of soft error changing the logic state of a Differential Logic with an Inverter Latch (DIL). Using Cadence Virtuoso, current pulses were injected into various nod...
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Main Authors: | , , , |
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Format: | Article |
Language: | English |
Published: |
UPM Press
2023
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Subjects: | |
Online Access: | http://ir.unimas.my/id/eprint/44815/1/Probability%20Formulation%20of%20Soft%20Error.pdf http://ir.unimas.my/id/eprint/44815/ http://www.pertanika.upm.edu.my/pjst/browse/regular-issue?article=JST-3732-2022 https://doi.org/10.47836/pjst.31.4.19 |
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